1. Field of the Invention
The present invention relates to a buried channel charge coupled device in which a built-in potential difference in a channel establishes potential wells that alternate with potential barriers in the channel upon the application of equal voltages to the gates. In particular, the invention relates to such a charge coupled device that includes means for charge reset that comprises constrictions in the thickness or the doping concentration of the well under the channel that are line-shaped when viewed in projection.
2. Description of Related Art
A charge coupled device sensor is known from U.S. Pat. No. 5,388,137 that has been issued on Feb. 7, 1995. The known device is suitable for use in the so-called AGP (=All Gates Pinning) operating mode, which renders it possible to suppress to a substantial degree the dark current which is largely determined by the surface states. In this way the unpleasant influence of local defects which are visible as white spots during display is largely eliminated as well. In order to obtain sufficiently large charge packages per pixel also in the AGP mode, the known device is provided with means for optimizing the potential profile in the channel whereby potential well in which charge can be stored alternating with potential barriers are formed in the channel upon the application of equal voltages to the gates. In the above patent it is proposed to use a voltage difference between the clock voltages which is substantially equal to, but opposed to the potential difference in the channel obtained by the doping profile, which potential difference is present for the purpose of charge integration in the integration time and is at least substantially eliminated during the transport phase. In this way a substantial difference in doping is allowed for, which makes it possible to increase the charge storage per pixel during the integration time while the surface is in inversion, so that the leakage currents can be kept low. In addition, electric charge may be removed from the transport channel (so called charge reset) before or during the integration time in that a positive voltage pulse is applied to the substrate. For localizing the charge reset, the above patent incorporates by reference U.S. Pat. No. 5,442,208 that has been issued on Aug. 15, 1995 and which discloses (see FIG. 2) line shaped restrictions in the thickness of the second layer positioned below the channel and running in the length direction thereof.
A disadvantage of the known device is that its maximum charge storage and optical sensitivity are still limited. This holds in particular if the pixel size is further reduced which is an ever present desire.